ADZS-21469-EZLITE【PDF 13/62 页】KIT EVAL EZ LITE ADSP-21469

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Preliminary Technical Data

ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469

PIN FUNCTION DESCRIPTIONS

The following symbols appear in the Type column of Table 7 :

A = asynchronous, I = input, O = output, S = synchronous,

(A/D) = active drive, (O/D) = open drain, and T = three-state,

(pd) = pull-down resistor, (pu) = pull-up resistor.

Table 7. Pin List

State

During

SSTL1 and After

Name

Type

LVTTL 8

Reset Description

AMI_ADDR 23–0

I/O/T

?

High-Z/

External Address. The ADSP-2146x outputs addresses for external

driven low memory and peripherals on these pins. The data pins can be multi-

(boot)

plexed to support the PDAP (I) and PWM (O). After reset, all

AMI_ADDR 23-0 pins are in EMIF mode and FLAG(0-3) pins will be in

FLAGS mode (default). When configured in the IDP_PDAP_CTL register,

IDP channel 0 scans the AMI_ADDR 23–0 pins for parallel input data.

AMI_DATA 7–0

I/O/T

?

High-Z

External Data. The data pins can be multiplexed to support the

external memory interface data (I/O), the PDAP (I), FLAGS (I/O) and PWM

(O). After reset, all AMI_DATA pins are in EMIF mode and FLAG(0-3) pins

will be in FLAGS mode (default).

DAI _P 20–1

I/O with fixed weak ?

pull-up on input

path 1, 2

High-Z

Digital Applications Interface . These pins provide the physical

interface to the DAI SRU. The DAI SRU configuration registers define the

combination of on-chip audiocentric peripheral inputs or outputs

connected to the pin and to the pin’s output enable. The configuration

registers of these peripherals then determine the exact behavior of the

pin. Any input or output signal present in the DAI SRU may be routed

to any of these pins. The DAI SRU provides the connection from the serial

ports, the S/PDIF module, input data ports (2), and the precision clock

generators (4), to the DAI_P20–1 pins.

DPI _P 14–1

I/O with fixed weak ?

pull-up only on

input path 1, 2

High-Z

Digital Peripheral Interface. These pins provide the physical interface to

the DPI SRU. The DPI SRU configuration registers define the combination of

on-chip peripheral inputs or outputs connected to the pin and to the pin’s

output enable. The configuration registers of these peripherals then deter-

mines the exact behavior of the pin. Any input or output signal present in the

DPI SRU may be routed to any of these pins. The DPI SRU provides the connec-

tion from the timers (2), SPIs (2), UART (1), flags (12), and general-purpose I/O

(9) to the DPI_P14–1 pins.

AMI_ACK

I (pu)

?

Memory Acknowledge (AMI_ACK). External devices can deassert

AMI_ACK (low) to add wait states to an external memory access.

AMI_ACK is used by I/O devices, memory controllers, or other periph-

erals to hold off completion of an external memory access.

AMI_RD

O/T 1, 2

?

High-Z

AMI Port Read Enable. AMI_RD is asserted whenever the ADSP-2146x

reads a word from external memory. AMI_RD has fixed internal pull-up

resistor.

AMI_WR

O/T 1, 2

?

High-Z

External Port Write Enable. AMI_WR is asserted when the ADSP-

2146x writes a word to external memory. AMI_WR has fixed internal

pull-up

resistor.

DDR2_ADDR 15–0

O/T

?

High-Z/

DDR2 Address. DDR2 address pins.

Driven low

Rev. PrC

| Page 13 of 62 | January 2009

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